Silicon defects form a costly pill for any semiconductor product company and smartly identifying these early on in the product life cycle is a silver bullet. Murphy’s law states that “Anything that can go wrong will go wrong”, hence the Design Verification Solutions are to be state-of-the-art in nature and should be carefully crafted to perceive the hidden bugs.
The Design Verification business unit within BlackPepper believes in working towards covering all the functional, code coverage while continuously improvising the IP, Sub-System and System Level Verification Environment. Our experienced team has a robust verification environment and our unique verification methodologies can aim at achieving zero defect silicon.
We provide support in the following areas.
• Experience of handling multimillion gate designs in Wireless, Automotive, Connectivity, Consumer Applications, Medical, IoT domains. • Full Chip/IP/Subsystem Verification Architecture development, Test Bench development and Functional verification. • High Speed IP/Subsystem Verification Architecture development, Test Bench development and Functional verification (Processors such as ARM, MIPS etc) • Full Chip Validation on parameters like latency, throughput, performance • Power Aware functional verification • Verification Flow and methodology support • Verification IP development and support. • Functional verification signoff (code coverage, functional coverage, formal verification, assertion, Gate-level simulation) • Emulation/Prototyping support and system/flow setup.