Openings

  • Physical Design - Sr. Engineer / Engineer

    Required Skill-set and Experience:
    • Block level floorplanning, power planning and IR drop analysis.
    • Timing closure with Xtalk and OCV
    • Multimode multi corner optimization and closure.
    • Clock tree synthesis and advanced clock tree implementation.
    • Block sizes upward of 400K Instances to 2M Instances.
    • Block level timing closure with sign off STA .
    • Scan chain reordering.
    • Block level ECO implementation involving netlist level logical changes.
    • Scripting experience in Perl/TCL.
    • Library performance analysis and fine tuning for implementation.
    • Excellent debugging skills in implementation issues and ability to come up with creative solutions .
    • Exposure to designs critical for power, area and timing at the same time.
    • Technologies from 90nm, 65nm, 40nm, 28nm, 20nm, 14nm, 10nm, 7nm.
    • In depth exposure in Implementation in any of the following platforms. - Cadence Innovus platform, Synopsys : ICC, ICC2
    • Tool Exposure in Sign Off
    • DRC/LVS : Calibre
      Timing sign off : Primetime/PrimeTime-SI
      Logical Equivalence : Conformal LEC
      Low Power Signoff : Conformal CLP
      IR Signoff : Ansys RedHawk

    Scripting & Programming Languages: Shell, PERL, TCL, AWK, sed, C
    EDA Tools: IC Compiler, Cadence Encounter, Primetime, Tweaker, Conformal LEC, Calibre, Star-RC
    Qualification: B.Tech or M.Tech in Electronics/Electrical Engineering with minimum of 3 years of strong, hands on experience in Physical Design.
    Must have handled Netlist to GDS II at block level for multiple tape outs.
    Experience: 3 - 5 years
    Location: Bangalore, US

  • Physical Design - Staff Engineer

    Required Skill-set and Experience:
    • Handled Netlist to GDS II at block level for multiple tape outs.
    • Expertise in hierarchical partitioning of block-level subsystems.
    • Hands on experience in implementing high performance cores, low power designs.
    • Blocks sizes upward of 400K Instances to 3M Instances.
    • Technologies from 65nm, 40nm, 28nm, 20nm, 14nm, 10nm, 7nm.
    • Exposure to designs concurrently critical on power, area and timing.
    • Flat timing closure of hierarchical subsytems with signoff STA .
    • Lead a team of engineers and owned the delivery responsibility
    • Block level floorplanning, power planning and IR drop analysis.
    • Timing closure with Xtalk and OCV
    • Multimode multi corner optimization and closure.
    • Clock tree synthesis and advanced clock tree implementation.
    • Scan chain reordering.
    • Block level ECO implementation involving netlist level logical changes.
    • Scripting experience in Perl/TCL.
    • Library performance analysis and fine tuning for implementation.
    • Excellent debugging skills in implementation issues and ability to come up with creative solutions .
    • Will be an advantage having hands on experience in implementing high performance cores, low power designs, exposure in top level implementation etc...
    • In depth exposure in Implementation in any of the following platforms.
    • Cadence Innovus platform
      Synopsys : ICC, ICC2

    • Tool exposure in Sign Off
    • DRC/LVS : Calibre
      Timing sign off : Primetime/PrimeTime-SI
      Logical Equivalence : Conformal LEC
      Low Power Signoff : Conformal CLP
      IR Signoff : Ansys RedHawk

    Scripting & Programming Languages: Shell, PERL, TCL, AWK, sed, C
    EDA Tools: IC Compiler, Cadence Encounter, Primetime, Tweaker, Conformal LEC, Calibre, Star-RC
    Qualification: B.Tech or M.Tech in Electronics/Electrical Engineering with minimum of 5 years of strong, hands on experience in Physical Design. Must have handled Netlist to GDS II at block level for multiple tape outs.
    Experience: 6 - 7 years
    Location: Bangalore, US

  • Physical Design - Sr. Staff Engineer

    Required Skill-set and Experience:
    • Lead, Managed large teams and delivered multiple first pass SOCs
    • Handled Netlist to GDS II at Top level/Hierarchical top level for multiple tape outs.
    • Top level die size estimation, floorplanning, power estimation, power planning.
    • IO Planning and package compatibility sign off.
    • ESD analysis on IO ring and signoff.
    • Netlist and constraint signin checks and validation.
    • PrimeTime constraint development at full chip level and clean up.
    • Design implementation environment setup.
    • Static and Dynamic power analysis at the top level.
    • Hierarchical chip planning, block planning, block level constraint development, hierarchical clock tree implementation, block integration and chip finishing.
    • GDS merge and sign off checks for tape out.
    • Ejob view.
    • Multimode multi corner optimization and closure at top level.
    • Clock tree synthesis and advanced clock tree implementation at full chip level.
    • Handling of PLL, TXR, DDR and other analog components during implementation.
    • IO ring customization for multi IO library implementation.
    • Handling of FlipChip RDL/AreaIO package
    • Full chips upward of 1M Instances to 40M+ instances.
    • Top level timing closure with sign off STA in MMMC with Xtalk and OCV.
    • Top level ECO implementation strategy development for netlist ,RTL and timing level changes
    • Methodology development, customization as per the specific design need.
    • Good hands own knowledge in reference flows.
    • Flow customization and fine tuning for Power, Performance, Area.
    • Exposure to DFM and DFM compatible implementation.
    • Library performance analysis and fine tuning for implementation.
    • Excellent debugging skills in implementation issues and ability to come up with creative solutions.
    • Technologies from 180nm, 130nm, 90nm, 65nm, 40nm, 28nm, 20nm, 14nm, 10nm, 7nm.
    • Expertise in Chiplevel RTL synthesis.
    • Exposure to Netlist formal verification.
    • Scripting experience in Perl/TCL.
    • Mastery level tool exposure in Implementation in any of the following platforms.
    • Cadence Innovus platform
      Synopsys : ICC, ICC2, DC/DC-T

    • Tool exposure in Sign Off
    • DRC/LVS : Calibre
      Timing sign off : Primetime/PrimeTime-SI
      Logical Equivalence : Conformal LEC
      Low Power Signoff : Conformal CLP
      IR Signoff : Ansys RedHawk, Pathfinder

    Scripting & Programming Languages: Shell, PERL, TCL, AWK, sed, C
    EDA Tools: IC Compiler, Cadence Encounter, Primetime, Tweaker, Conformal LEC, Calibre, Star-RC
    Qualification: B.Tech or M.Tech in Electronics/Electrical Engineering with minimum of 7 years of strong, hands on experience in Physical Design. Must have handled Netlist to GDS II at Top level or Hierarchical top level for multiple tape outs..
    Experience: 9 - 12 years
    Location: Bangalore, US

  • RTL Design - Sr. Engineer / Engineer

    Required Skill-set and Experience:
    • Experience in Logic Design, Micro-architecture and RTL coding is a must.
    • Expertise in Verilog is a must. Expertise in VHDL/SystemVerilog desirable
    • Experience in RTL Quality Assurance is a must - Linting / Clock-Domain-Crossing / Design Assertions coding
    • Experience in supporting implementation teams is desirable - Functional coverage analysis / Timing closure / DFT logic insertion
    • Experience with implementing DSP algorithms in hardware is desirable
    • Experience with one or more bus protocols is desirable (PCIe, AXI, AHB, APB, Wishbone)
    • Experience with implementation in Xilinx / Altera FPGAs is desirable.
    • Experience with IP configuration and SoC integration is desirable.

    Qualification: B.Tech or M.Tech in Electronics/Electrical Engineering with minimum of 3 years of experience.
    Experience: 2 - 6 years
    Location: Bangalore

  • RTL Design - Sr. Staff Engineer / Staff Engineer

    Required Skill-set and Experience:
    • Experience in Logic design, Architecture, Coding is a must
    • Experience in one or more key technical areas such as ARM-based SoCs, multi-processor systems, Graphics sub-systems and Video sub-systems is a must
    • Thorough knowledge of bus protocols (such as PCIe, AMBA or Wishbone) and standard memory interfaces (such as DDR3) is a must
    • Experience in ensuring delivery commitments to clients is a must
    • Experience in interacting with client representatives on technical / project-management / project proposal aspects is a must
    • Exposure to IP-level, sub-system-level and full-chip level design aspects is desirable
    • Experience in low power design is desirable
    • Experience in working with FPGA platforms and emulator systems (Veloce, Palladium etc.) is desirable
    • Familiarity with DFT structures such as scan, MBIST, LBIST and JTAG is desirable
    • Experience in coaching junior members of the team is desirable
    • Experience in contributing to internal activities related to hiring, training and process compliance is desirable

    Qualification: B.Tech or M.Tech in Electronics/Electrical Engineering with minimum of 6 years of experience.
    Experience: 7 - 13 years
    Location: Bangalore

  • RTL Design - Principal Engineer

    Required Skill-set and Experience:
    • Experience in Spec-to-Silicon implementation - Chip architecture, Design Partitioning, IP selection, RTL integration and Hand-off to Physical design - is a must
    • Experience in support for DFT insertion, Simulation, Formal Verification and Timing sign-off is a must
    • Hands-on experience in EDA tools covering simulation, synthesis, linting and CDC is a must
    • System expertise in one or more technology domains - eg. IoT, Automotive and Wireless connectivity - is a must
    • Ability to provide direction and drive internal activities related to project proposals, client interactions, training and process compliance is a must
    • Experience in IP-level, sub-system-level and full-chip level design aspects is a must
    • Experience in industry-standard architectures / systems eg. ARM, OMAP, multi-processor systems, Graphics sub-systems or Video subsystems is a must
    • Experience in low power design is a must
    • Experience in working with FPGA platforms and emulator systems (Veloce, Palladium etc.) is desirable
    • Experience in high-capacity FPGAs of Altera/Xilinx is desirable
    • Awareness of Software systems, Industrial Design and Board Design aspects is desirable.

    Qualification: B.Tech or M.Tech in Electronics/Electrical Engineering with minimum of 12 years of experience.
    Experience: 13+ years
    Location: Bangalore

  • ASIC Verification - Sr. Engineer / Engineer

    Required Skill-set and Experience:
    • Good experience in Develop, Debug and maintain complex IP, Sub-System and SoC environment using UVM/SV/C/C++.
    • Good experience Functional and Code coverage closer.
    • Good experience in processor-driven verification, Should have good knowledge of SoC Bus protocols.
    • Good experience with assertion based verification techniques.
    • Experience in scripting (shell, PERL, TCL), automation and regression management.
    • Ability to communicate effectively with multiple global cross-functional teams.

    Scripting & Programming Languages: Shell, PERL, TCL, Python
    EDA Tools: Mentor Questa, Cadence NC, Synopsys VCS
    Qualification: B.Tech or M.Tech in Electronics/Electrical Engineering with minimum of 3 years of experience.
    Experience: 3 - 5 years
    Location: Bangalore

  • ASIC Verification - Sr. Staff Engineer / Staff Engineer

    Required Skill-set and Experience:
    • Strong in RTL verification using Verilog, System Verilog. VHDL knowledge is a plus.
    • Strong in UVM / OVM / VMM based verification methodologies.
    • Strong in Test architecture, Test plan creation, Test bench creation, Test case creation.
    • Strong in Functional and Code coverage definition and analysis.
    • Strong in IP level, sub-system level and full-chip verification .
    • Hands-on experience in C/C++ based test case development.
    • Must have experience in processor-driven and BFM driven verification.
    • Must have experience developing BFMs and monitors.
    • Must have experience with Industry standard Verification IP (VIP) integration and use.
    • Must have experience with assertion based verification techniques. Knowledge in other formal verification techniques is a plus.
    • Must have experience with verifying low power (LP) SoCs (containing LP enabling structures like on-die power-switches).
    • Must have experience working with emulator boxes (eg. Veloce, Palladium) and FPGA platforms.
    • Experience in ARM-based SoC verification is a must. Should have expert knowledge of AMBA protocols.
    • Experience in scripting (shell, PERL, TCL), automation and regression management.
    • Experience in verification of Design-for-Test structures (eg. scan, MBIST, LBIST, JTAG).
    • Experience in full-timing annotated gate level verification of SoCs.
    • Experience in high-speed serial protocols (eg. PCI-express).
    • Experience in high-speed on-chip buses / NoCs.
    • Experience in verification of high-speed memory interfaces (eg DDR3).
    • Experience in verification of CPU, Graphic, Video sub-systems is a plus.
    • Knowledge of Mixed-Signal Verification is a plus.
    • Knowledge of DSP-based / signal-processing verification (eg. MATLAB drive, bit-true verification) is a plus.
    • Knowledge of System-C is a plus.
    • Excellent debugging skills.
    • Excellent communication skills and the ability to lead and be part of large teams.
    • Excellent documentation skills (Word, Visio).

    Scripting & Programming Languages: Shell, PERL, TCL, Python
    EDA Tools: Mentor Questa, Cadence NC, Synopsys VCS
    Qualification: B.Tech or M.Tech in Electronics/Electrical Engineering with minimum of 6 years of experience.
    Experience: 6 - 12 years
    Location: Bangalore

  • Synthesis/STA - Sr. Staff Engineer

    Required Skill-set and Experience:
    • Handled Synthesis & Timing closure on multiple designs with varying complexities.
    • Lead and Managed large synthesis, STA teams on multiple tapeouts.
    • Synthesis, STA Flow Development and automation
    • Chip level Constraint Development & Validation
    • Multimode and Physical synthesis & timing closure of hierarchical designs > 25M Instances
    • Performed Power Aware synthesis for designs with multiple power domains.
    • Experience in handling the automated timing ECO generation flow using industry tools
    • Expertise in timing closure on critical IO Interfaces like DDR, RGMII, PCI-Express
    • Expertise in timing closure of designs on all metrics including (Corner based Frequency/DRV, Leakage) across corners/modes > 100
    • Good Understanding of RTL-Netlist formal verification and Static Low Power Checks.
    • Exposure to designs concurrently critical on power, area and timing..
    • Experience of working on 180nm, 90nm, 65nm, 40nm, 28nm , 14nm , 10nm, 7nm.
    • Mastery level tool exposure in Implementation in any of the following platforms.
    • Cadence Genus platform
      Synopsys : DC/DC-T

    • Tool exposure in Sign Off
    • Timing sign off : Primetime/PrimeTime-SI, Tempus
      Logical Equivalence : Conformal LEC
      Low Power Signoff : Conformal CLP

    Scripting & Programming Languages: Shell, PERL, TCL, AWK, sed, C
    EDA Tools: PrimeTime, PT-SI, Tweaker, Design Compiler, Conformal LEC, VCS/Modelsim/NCSim
    Qualification: B.Tech or M.Tech in Electronics/Electrical Engineering with minimum of 10 years of experience.
    Experience: 10+ years
    Location: Bangalore, US

  • DFT - Sr. Engineer / Engineer

    Required Skill-set and Experience:
    • Must have worked in at least 1 DFT project
    • Good Understanding of Fault models, Scan, ATPG and pattern simulation
    • Knowledge of BIST, MBIST and Boundary Scan is a plus.
    • Awareness of DFT techniques JTAG, TAP, MBIST, P1500, IEEE 1149 standards, Core-Based Testing Standards
    • Experience in simulation on zero delay and SDF
    • Should have working knowledge of Verilog code
    • Should have working knowledge of Shell, TCL and perl scripts.
    • Experienced in industry standard tools viz. Mentor/Cadence

    Scripting & Programming Languages: Shell, PERL, TCL, AWK, sed, C
    EDA Tools: Tessent, DFTMAX, Tetramax, VCS/Modelsim/NCSim, Primetime
    Qualification: B.Tech or M.Tech in Electronics/Electrical Engineering with minimum of 3 years of experience.
    Experience: 2-6 years
    Location: Bangalore

  • DFT - Staff Engineer

    Required Skill-set and Experience:
    • Experience in leading DFT and ATPG activities on SoC with a team of 2-6 engineers
    • Expertise in MBIST Planning/Insertion, Partitioning Design for Scan, Scan Insertion, Compression, Wrapper Insertion, ATPG Simulations
    • Expertise in flat/hierarchical DFT methodologies and implementation
    • Must know JTAG, TAP, IEEE 1149 standards.
    • Strong knowledge of DFT techniques like JTAG, MBIST, P1500, Core-Based Testing Standards, scan, on-chip scan compression, fault models, ATPG, fault simulation and AC scan for at speed testing
    • Expertise in coverage improvement and debugging skills
    • Should have working knowledge of Verilog code
    • Should have working knowledge of Shell, TCL and perl scripts.
    • Experienced in industry standard tools viz. Mentor/Cadence

    Scripting & Programming Languages: Shell, PERL, TCL, AWK, sed, C
    EDA Tools: Tessent, DFTMAX, Tetramax, VCS/Modelsim/NCSim, Primetime
    Qualification: B.Tech or M.Tech in Electronics/Electrical Engineering with minimum of 6 years of experience.
    Experience: 6 - 9 years
    Location: Bangalore

  • Analog Layout - Staff Engineer

    Job Description:
    • Work independently on Analog layout design of block level and chip level from schematics.
    • Candidate should be able to handle project independently and provide timelines.
    • Leading the team and providing good quality results.
    • Required Skill-set and Experience:
    • Good understanding of Mosfet-s, Bipolar and other basic devices.
    • Hands on experience in Analog Layout design of various designs Linear and Switching regulators, SerDes, LVDS, DDR Phy, PLL and analog building blocks amplifiers, comparator, oscillator, voltage, current reference circuits etc.
    • Understanding of different layout concepts like matching, shielding etc.
    • Should have prior work experience in CMOS process technologies - 22nm, 28nm, 45nm, 65nm etc.
    • Hands on experience in FINFET technology will be an added advantage
    • Good understanding of deep sub-micron and DFM issues.
    • Thorough working knowledge of layout design and physical verification tools using Cadence Virtuoso layout suite, Mentor Calibre, Synopsys Hercules etc.
    • Scripting knowledge of perl & cadence SKILL will be added advantage.

    Qualification: B.Tech or M.Tech in Electronics/Electrical Engineering with minimum of 6 years of experience.
    Experience: 6 - 9 years
    Location: Bangalore

  • Analog Layout - Sr. Engineer / Engineer

    Job Description:
    • Work independently on Analog layout design of block level and chip level from schematics.
    • Candidate should be able to handle block independently and timely completion is expected.
    • Good communication skills.
    • Required Skill-set and Experience:
    • Good understanding of Mosfet-s, Bipolar, LDMOS and other basic devices’ cross sections.
    • Hands on experience in Analog Layout design of various designs Linear and Switching regulators, SerDes, LVDS, DDR Phy, PLL and analog building blocks amplifiers, comparator, oscillator, voltage, current reference circuits etc.
    • Understanding of different layout concepts like matching, shielding etc.
    • Should have prior work experience in CMOS process technologies - 22nm, 28nm, 45nm, 65nm etc.
    • Hands on experience in FINFET technology 16nm,7nm, 5nm & High voltage BCDMOS will be an added advantage
    • Good understanding of deep sub-micron and DFM issues.
    • Thorough working knowledge of layout design and physical verification tools using Cadence Virtuoso layout suite, Mentor Calibre, Synopsys Hercules etc.
    • Scripting knowledge of perl & cadence SKILL will be added advantage

    Qualification: B.Tech or M.Tech in Electronics/Electrical Engineering with minimum of 6 years of experience.
    Experience: 3 - 6 years
    Location: Bangalore

  • Analog Circuit Design - Staff Engineer

    Job Description:
    • Work independently on Analog Circuit design of block level and chip level from schematics.
    • Candidate should be able to handle project independently and provide timelines.
    • Leading the team and providing good quality results.
    • Required Skill-set and Experience:
    • Good understanding of Mosfet-s, Bipolar and other basic devices.
    • Hands on experience in Analog Circuit design of various designs Linear and Switching regulators, SerDes, LVDS, DDR Phy, PLL and analog building blocks amplifiers, comparator, oscillator, voltage, current reference circuits etc.
    • Experience in high voltage BCDMOS for power management and lower nodes & FinFet for high speed design.
    • Good understanding of deep sub-micron and DFM issues.
    • Thorough working knowledge of Circuit design EDA tools using Cadence Virtuoso suite, fast spice simulators, co-sim & verilogA modelling etc.
    • Supporting post silicon validation team.

    Qualification: B.Tech or M.Tech in Electronics/Electrical Engineering with minimum of 6 years of experience.
    Experience: 6 - 9 years
    Location: Bangalore

  • Analog Circuit Design - Sr. Engineer / Engineer

    Job Description:
    • Work independently on Analog Circuit design of block level from specifications.
    • Should be able to handle design block independently.
    • Should have strong problem solving skills.
    • Required Skill-set and Experience:
    • Good understanding of Mosfet-s, Bipolar and other basic devices.
    • Hands on experience in Analog Circuit design of various designs Linear and Switching regulators, SerDes, LVDS, DDR Phy, PLL and analog building blocks amplifiers, comparator, oscillator, voltage, current reference circuits etc.
    • Experience in high voltage BCDMOS for power management and lower nodes & FinFet for high speed design.
    • Good understanding of deep sub-micron and DFM issues.
    • Thorough working knowledge of Circuit design EDA tools using Cadence Virtuoso suite, fast spice simulators, co-sim & verilogA modelling etc.
    • Supporting post silicon validation team.
    • Should have expertise in running PVT corner, Montecarlo and PEX simulation using ADE-XL.

    Qualification: B.Tech or M.Tech in Electronics/Electrical Engineering with minimum of 6 years of experience.
    Experience: 3 - 6 years
    Location: Bangalore

  • Memory Characterization - Sr. Engineer / Engineer

    Job Description:
    • Contribute towards Design and Development of Single/Multiport SRAM, Register file compilers in 28nm/16FF/7FF Technologies.
    • Circuit design/simulation of key components such as bitcell, WL decoder, SAMP, Column decoder and control logic.
    • Development of critical path and characterization flow to perform detailed margin and characterization simulations.
    • Statistical Analysis of Bit-Cell and Sense Amplifier and Self Time Blocks for Compiler Target yield Sign-Off
    • Design Tuning, Margin Analysis and Sign-Off for Complete Compiler to meet Yield and Performance targets.
    • Logic simulations and detailed timing analysis of key paths in high speed memory design.
    • Signal-Integrity (EM) and Power-Integrity (IR drop) analysis and design.
    • Required Skill-set and Experience:
    • Expertise of high speed/low power CMOS circuit design , clocking scheme, Static and dynamic logic circuits.
    • Experience in Designing and Driving one or Memory Compilers Specifications to final release.
    • Complete hands on experience in using Cadence/Mentor schematic/layout editor tools.
    • Complete hands on experience with Circuit simulation tools such as HSPICE, HSIM, XA, Spectre, XPS and waveform viewer tools such as Simvision, Custom Explorer etc.
    • Experience in Shell/Perl/Python Scripting is a strong plus.
    • Experience in Understanding the layout design issues in sub nanometer regime is a Plus.

    Qualification: B.Tech or M.Tech in Electronics/Electrical Engineering with minimum of 3 years of experience.
    Experience: 3 - 8 years
    Location: Bangalore

  • Firmware Development & Linux - Sr. Engineer / Engineer

    Job Description:
    • Design and implement software for embedded devices and systems from requirements to production/deployment
    • Design, develop, code, test and debug system software
    • Required Skill-set and Experience:
    • Excellent knowledge of Linux/RTOS coding techniques, interfaces and hardware subsystems knowledge of reading schematics and data sheets for components
    • Hands on Experience in development and debugging of software on embedded targets
    • Excellent knowledge of Linux/RTOS coding techniques, interfaces and hardware subsystems
    • Experience in Linux/RTOS Kernel and debugging
    • One or more of the below
    • Development experience in Firmware, BSP and Device Drivers
      Board Bring up and experience with Boot loaders, Bootloader development and porting/migration
      DSP Algorithm implementation, performance optimization
      Device Driver development and porting across RTOS or versions (WiFi/WLAN, BT, USB, HDMI, PCI/PCIe, SPI/SDIO, SATA, I2C, I2S etc)

    • Experience working with Opensource Software
    • Domain Specific Experience : Automotive, Medical, IoT, Multimedia, Consumer, Defence
    • OS : Linux or any RTOS
    • Language : Proficient in C/C++. Python (Good to Have)
    • Tools : JTAG, Embedded IDEs & Toolchain, Logic analyser/CRO/Protocol Analyzer (Good to Have)
    • Familiarity with software configuration management tools, defect tracking tools, and peer review

    Qualification: B.Tech or M.Tech in Electronics/Electrical/Computer Engineering with minimum of 3 years of experience.
    Experience: 3 - 7 years
    Location: Bangalore

  • Machine Learning - Staff Engineer / Sr. Engineer / Engineer

    Job Description:
    • Working on Vision and Sensor Fusion Systems focusing on Automotive (ADAS) and IoT (Machine Condition Monitoring)
    • Required Skill-set and Experience:
    • Excellent knowledge in different deep learning practices (CNN, RNN, LTSM, Reinforcement Learning, SSD, Inception, GoogleNet, YOLO etc.) as well as Machine Learning in general
    • Machine Learning Programming
    • Expert experience with computer vision and image processing (OpenCV, openCV CUDA)
    • Experience with Caffe, Tensorflow or other model training software.
    • Fluent in Python and C/C++ on a Linux platform
    • Good to Have
    • Object detection and classification DNN models
      Experience in using Nvidia AI boards, Intel NCS, or any other low power embedded device for inference is an added advantage.
      Contribution in research communities, publishing papers or participation in Github projects related to deep learning is preferred

    • Advanced degree (PhD, Post Graduation) in machine learning or computer science
    • Embedded Experience is a plus

    Qualification: B.Tech or M.Tech in Electronics/Electrical/Computer Engineering with minimum of 3 years of experience.
    Experience: 3 - 12 years
    Location: Bangalore

  • DSP & Algorithms - Staff Engineer / Sr. Engineer / Engineer

    Job Description:
    • Develop/Maintain sensor fusion and object detection algorithms
    • Create, develop, invent, validate and integrate sensor fusion and object detection algorithms
    • Evaluates system capability and overall conformance to requirements and works with partitions to address deficiencies.
    • Establish and develop relationships with collaborating suppliers and external entities to meet project goals.
    • Evaluates and recommends options consistent with industry best practices.
    • Required Skill-set and Experience:
    • Expertise in C/C++, Python
    • Experience in one or more of the following areas related to sensor fusion
    • Basics of signal processing and Sensor fusion techniques.
      System integration and signal processing of radar, lidar, camera, ultrasonics, 3D depth / TOF sensors, GPS, IMU
      Algorithm development for environment and situation awareness using multi-sensor fusion, object detection (point cloud processing, association, classification and tracking of multiple objects in complex, 3D environment)
      Non-linear optimization / Iterative Closet Point (ICP)
      Probabilistic filters (particle filters, Kalman filters)

    • Experience in software optimization (in prototype and embedded target environment)
    • Fixed point implementation knowledge .
    • ARM processors expertise along with libraries like CMSIS is added advantage.
    • Strong problem-solving, organizational, analytical and root cause skills.
    • SIMD/NEON implementation knowledge.
    • Good understanding on IMU (Accelerometers/Gyroscopes) and other sensors .
    • Conduct detailed analysis, simulation and testing of prototype
    • Demonstrates strong teamwork skills
    • Communicates directly with his or her direct management and cross-functional leaders as required.
    • Preferred Qualifications
    • Masters degree in a related field of study
      Experience of 5+ in signal processing and/or sensor, embedded platform areas.
      Experience with Python
      Experience with Connectivity technologies like BT/BLE, Sub GHz
      Experience with embedded development platforms (Cuda, Nvidia, Renesas, TI)
      Learner in AI/ML areas will be added advantage.

    Qualification: B.Tech or M.Tech in Electronics/Electrical/Computer Engineering with minimum of 3 years of experience.
    Experience: 3 - 12 years
    Location: Bangalore

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