Openings

  • Sr. Engineer - Physical Design

    Job Description:
    • Handled Netlist to GDS II at block level for multiple tape outs.
    • Hands on experience in implementing high performance cores, low power designs.
    • Blocks sizes upward of 400K Instances to 2M Instances
    • Technologies from 65nm, 40nm, 28nm, 20nm, 14nm, 10nm.
    • Block level floorplanning, power planning and IR drop analysis.
    • Timing closure with Xtalk and OCV
    • Multimode multi corner optimization and closure.
    • Clock tree synthesis and advanced clock tree implementation.
    • Block level timing closure with sign off STA .
    • Scan chain reordering.
    • Block level ECO implementation involving netlist level logical changes.
    • Library performance analysis and fine tuning for implementation.
    • Excellent debugging skills in implementation issues and ability to come up with creative solutions .

    Scripting & Programming Languages: Shell, PERL, TCL, AWK, sed, C
    EDA Tools: IC Compiler, Cadence Encounter, Primetime, Tweaker, Conformal LEC, Calibre, Star-RC
    Experience: 4-5 years
    Location: Bangalore, Singapore, US

  • Lead Engineer - Physical Design

    Job Description:
    • Handled Netlist to GDS II at block level for multiple tape outs.
    • Expertise in hierarchical partitioning of block-level subsystems.
    • Hands on experience in implementing high performance cores, low power designs.
    • Blocks sizes upward of 400K Instances to 3M Instances.
    • Technologies from 65nm, 40nm, 28nm, 20nm, 14nm, 10nm.
    • Exposure to designs concurrently critical on power, area and timing.
    • Flat timing closure of hierarchical subsystems with signoff STA.
    • Lead a team of engineers and owned the delivery responsibility.
    • Block level floorplanning, power planning and IR drop analysis.
    • Timing closure with Xtalk and OCV
    • Multimode multi corner optimization and closure.
    • Clock tree synthesis and advanced clock tree implementation.
    • Scan chain reordering.
    • Block level ECO implementation involving netlist level logical changes.
    • Library performance analysis and fine tuning for implementation.
    • Excellent debugging skills in implementation issues and ability to come up with creative solutions.

    Scripting & Programming Languages: Shell, PERL, TCL, AWK, sed, C
    EDA Tools: IC Compiler, Cadence Encounter, Primetime, Tweaker, Conformal LEC, Calibre, Star-RC
    Experience: 5-7 years
    Location: Bangalore, Singapore, US

  • Technical Lead - Synthesis/STA

    Job Description:
    • Handled Synthesis & Timing closure on multiple designs with varying complexities.
    • Lead teams on design and development of ASIC, FPGA designs, Synthesis, STA.
    • Synthesis, STA Flow Development and automation
    • Chip level Constraint Development & Validation
    • Expert in Signal Integrity Analysis
    • Multimode synthesis & timing closure of hierarchical designs > 25M Instances
    • Performed CPF/UPF Aware synthesis for designs with multiple power domains.
    • Experience in handling the automated timing ECO generation flow using industry tools.
    • Expertise in timing closure on critical IO Interfaces like DDR, PCI-Express.
    • Exposure to Logic Design & RTL Coding.
    • Exposure to DDR, NAND Flash, SRAM memory controller usage
    • Expertise in timing closure of designs on all metrics including (Corner based Frequency/DRV, Leakage) across corners/modes > 100
    • Exposure to simulation at RTL and gate level
    • Expertise in RTL-Netlist formal verification.
    • Exposure to designs concurrently critical on power, area and timing.
    • Experience of working on 28nm and below

    Scripting & Programming Languages: Shell, PERL, TCL, AWK, sed, C
    EDA Tools: PrimeTime, PT-SI, Tweaker, Design Compiler, Conformal LEC, VCS/Modelsim/NCSim
    Experience: 10+ years
    Location: Bangalore, Singapore, US

  • Technical Director - Physical Design

    Job Description:
    • Handled RTL to GDS II at Top level/Hierarchical top level for multiple tape outs.
    • Top level die size estimation, floorplanning, power estimation , power planning
    • Lead, managed large teams and delivered multiple first pass SOCs
    • IO Planning and package compatibility sign off.
    • ESD analysis on IO ring and signoff.
    • Netlist and constraint sign-in checks and validation.
    • PrimeTime constraint development at full chip level and clean up.
    • Design implementation environment setup.
    • Static and Dynamic power analysis at the top level.
    • Hierarchical chip planning, block planning, block level constraint development, hierarchical clock tree implementation, block integration and chip finishing.
    • GDS merge and sign off for tape out.
    • Ejob view
    • Multimode multi corner optimization and closure at top level.
    • Clock tree synthesis and advanced clock tree implementation at full chip level.
    • Handling of PLL, TXR, DDR and other analog components during implementation.
    • IO ring customization for multi IO library implementation.
    • Handling of FlipChip RDL/AreaIO package
    • Full chips upward of 1M Instances to 40M+ instances.
    • Top level timing closure with sign off STA in MMMC with Xtalk and OCV.
    • Top level ECO implementation strategy development for netlist ,RTL and timing level changes
    • Methodology development, customization as per the specific design need.
    • Good hands-on knowledge in reference flows.
    • Flow customization and fine tuning for Power, Performance, Area.
    • Expertise in DFM and DFM compatible implementation.
    • Library performance analysis and fine tuning for implementation.
    • Excellent debugging skills in implementation issues and ability to come up with creative solutions.
    • Technologies down to 14nm and below
    • Expertise in Chiplevel RTL synthesis.
    • Expertise in Netlist formal verification.

    Scripting & Programming Languages: Shell, PERL, TCL, AWK, sed, C
    EDA Tools: ICC, Olympus, Encounter, Primetime, PT-SI, DC/DC-T, Calibre, Star-RC
    Experience: 15+ years
    Location: Bangalore

  • Engineer - DFT

    Job Description:
    • Strong knowledge of ATPG pattern generation & verification
    • Awareness of DFT techniques JTAG, MBIST, P1500, Core-Based Testing Standards
    • Good experience with any commercial ATPG & Simulation EDA Tools
    • Experience with any commercial MBIST & JTAG solution
    • Experience in simulation on zero delay and SDF
    • Excellent debug skills
    • Excellent communication skills
    • Can execute tasks independently as well as be part of a team

    Scripting & Programming Languages: Shell, PERL, TCL, AWK, sed, C
    EDA Tools: Tessent, DFTMAX, Tetramax, VCS/Modelsim/NCSim, Primetime
    Experience: 2-4 years
    Location: Bangalore, Singapore

  • Sr. Engineer - DFT

    Job Description:
    • Strong knowledge of DFT techniques like JTAG, MBIST, P1500, Core-Based Testing Standards, scan, on-chip scan compression, fault models, ATPG, fault simulation and AC scan for at speed testing
    • Good experience with any commercial ATPG & Simulation EDA Tools
    • Good experience with any commercial scan, MBIST & JTAG solution
    • Experience in simulation on zero delay and SDF
    • Excellent debug skill
    • Ability to communicate effectively with multiple global cross-functional teams
    • Can execute tasks independently as well as be part of a team

    Scripting & Programming Languages: Shell, PERL, TCL, AWK, sed, C
    EDA Tools: Tessent, DFTMAX, Tetramax, VCS/Modelsim/NCSim, Primetime
    Experience: 4-6 years
    Location: Bangalore, Singapore

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You can also mail your CV to us at career@blackpeppertech.com